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The following appendix is being filed with this application, the entire contents of which are herein incorporated by reference for all purposes:
Appendix A (127 pages)xe2x80x94CircuitScope User Guide.
The present invention relates to the field of electronic design automation, and more particularly to techniques, including methods, system, and computer code, for performing analysis of circuit designs based on assertions.
The typical design methodology for integrated circuit designs such as very large scale integrated (VLSI) circuits, application specific integrated circuits (ASICs), and so on, is conventionally divided into the following three stages: first a design capture step is performed using for example a high level language synthesis package. Next, design verification is made on the resulting design. This includes simulations, timing analysis, automatic test pattern generation (ATPG) tools, and so on. Then, there is layout and eventual tape out of the device. The device is then tested and the process may need to be reiterated one or more times until the desired design criteria are satisfied.
Currently, electronic design automation (EDA) tools are used to define and verify prototype systems. Conventional EDA tools provide computer-aided facilities for electronic engineers to define prototype designs, typically by generating either netlist files, which specify components and their interconnections, or hardware description files, which specify prototype system functionality according to a hardware description language (HDL).
Initially, the desired functionality for a circuit is analyzed by one or more designers. They define the logical components of the circuit and their interactions by specifying the logic design using design capture tools.
Two common methods for specifying the design are schematic capture and hardware description languages. Both of these methods allow a circuit designer to specify the circuit at the register transfer level. The schematic capture method provides a user interface which allows a logic circuit to be drawn in graphical form on a computer display. Using this method, the circuit is defined as small building blocks, which can be used to develop higher level designs with increasing degrees of abstraction.
Encoding the design in a hardware description language (HDL) is the other major design entry technique used to specify modern integrated circuits. Hardware description languages are specially developed to aid a designer in describing a circuit. The HDL program specifying the design may be compiled into the same data format produced by schematic capture. This capability provides the designer great flexibility in methods used for specifying a logic design.
Next, it is necessary to verify that the logic definition is correct and that the circuit implements the function expected by the designers. Typically, this involves timing analysis and simulation tools. The data representation in the logic design database may be reformatted as needed prior to use by the timing analysis and simulation tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the device resulting from the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the design as needed. These design iterations help to ensure that the design satisfies its requirements.
Other verification methods include generating software models of the logic circuit design and testing the software model of the design with designer-specified test cases. Because it is not possible to check every possible condition which may be generated in the actual logic design, faulty logic may remain because it would not have been exercised by any of the test cases. Errors in the logic design may remain undetected until the release of a product on the marketplace, where it may cause costly redesigns.
Formal verification is another way to check logic design prior to the fabrication of a device. Formal verification is a technique wherein a logic circuit is modeled as a state transition system, and specifications are provided for components in the system. One way in which specifications may be made is through the use of logic formulas. Each of the components in the logic design is specified, and all possible behaviors of the design may be exercised by a tool which confirms that these specifications are met.
Once a netlist has been generated, there are a number of commercially available silicon compilers, also called place and route tools, that are used to convert the netlist into a semiconductor circuit layout. The semiconductor circuit layout specifies the physical implementation of the circuit in silicon or other semiconductor materials.
As can be seen, the design verification step can be quite resource intensive in terms of computational requirements and time. When large and very large scale integrated circuits are considered, the data size requirements can easily exceed the capacity of present day computer technology. Consequently, the inability to make such tests can lead to missed design errors. In addition, many run-time tools are non-linear, making design iterations expensive in terms of time and resource allocation. While there are industry formats and commercial products for describing and checking the layout rules, we are not aware of any corresponding commercially available products to address circuit rule verification which are flexible and can be easily customized for circuit analysis.
Market requirements are driving chip designers to integrate ever higher levels of functionality on silicon. Doing this within the manufacturing guidelines and within the market window of opportunity is the key challenge facing designers today. Though deeper sub-micron feature sizes allow greater integration, the technology brings with it circuit and interconnect issues which exacerbate the problems designers must overcome. This increases the likelihood of unpredictable side effects which leads to costly design iterations and sometimes malfunctioning products.
What is needed is a design tool which can overcome the computational costs of conventional brute-force simulation methods. It is desirable to provide a design tool which facilitates locating and repairing circuit integrity failure points. The design tool should also facilitate locating and correcting noise failure conditions. What is needed is a design tool that can reduce failure conditions in the early phases of a design cycle and so reduce the number of needed design iterations, while at the same time improving the quality of the design.
The present invention provides techniques for locating and repairing integrity problems associated with circuit designs including complex deep submicron (DSM) integrated circuit (IC) designs. The techniques according to the present invention perform fast and exhaustive analysis of circuit designs based on circuit rules or xe2x80x9cassertionsxe2x80x9d which encapsulate a circuit designer""s assumptions and expectations of a good circuit design. By performing the analysis at the pre-layout and/or post-layout phase, the present invention reduces the need for extensive back-end circuit and timing simulations while assuring greater probability of success with first silicon of circuit design. The present invention provides an enhanced circuit design methodology which increases the predictability of the circuit design, which significantly reduces design iterations typically associated with conventional analysis techniques, and which in turn reduces the time to market.
According to an embodiment, the present invention receives circuit design information describing the circuit design to be analyzed, assertions associated with circuit structures in the circuit design, and checks to be applied to the circuit design. An assertion is associated with a circuit structure and specifies a context of the circuit design in which the circuit structure is to be analyzed, an attribute associated with the circuit structure, and a constraint associated with the attribute. The present invention analyzes the circuit design based on the check and the assertion to generate analysis results data which identifies one or more instances of the circuit structure in the circuit design which do not satisfy the constraint specified in the assertion.
According to another embodiment of the present invention, the assertion associated with a circuit structure also indicates an action to be performed if the circuit structure does not satisfy the constraint specified in the assertion. According to an embodiment, the present invention performs the action when an assertion violation is identified. Examples of actions include generating a circuit representation of a portion of the circuit design including instances of the circuit structure which do not satisfy the constraint specified in the assertion, performing further analysis on the circuit representation, generating stimuli for analyzing the circuit portion, and the like.
According to yet another embodiment, the present invention generates reports based on the assertion-based analysis. These reports may identify instances of circuit structures which violate one or more assertions associated with the circuit structures. The reports may also list information about the circuit structures included in the circuit design.
According to another embodiment of the present invention, the context information specified in an assertion indicates a driver structure and a receiver structure connected either serially or in parallel to the circuit structure under analysis. The driver structure drives signals to the circuit structure under analysis and may comprise one or more circuit structures. The receiver structure receives signals from the circuit structure under analysis and may also comprise one or more circuit structures.
According to yet another embodiment, the present invention provides features for automatically detecting missing assertions. The present invention identifies and flags circuit structures for which no assertions have been specified. This identification may be performed at various hierarchical levels of circuit structures and helps reduce unexpected design errors associated with the circuit design. This feature of the present invention also helps identify circuit structures which may have been inadvertently introduced in the circuit design.
According to another embodiment, the present invention extracts transistor-level information from the circuit design information. The present invention then determines the signal flow direction in the circuit design. The present invention. identifies a plurality of circuit structures from the transistor-level information. The circuit structures may then be classified according to a hierarchical classification of circuit structure classes. Assertions may be associated with the classes of circuit structures such that a circuit structure class inherits assertions from all its ancestor classes. Assertions associated with a circuit structure include those assertions which have been specified for the circuit structure class to which the circuit structure belongs and assertions which have been inherited by the circuit structure class.
The foregoing, together with other features, embodiments, and advantages of the present invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.